Virtual Labs

a:

b:

c:

d:

a:

b:

c:

d:

a: Series connection of n-devices with input A and input B b: Parallel connection of p-devices with input A and input B c: Combination of series and parallel connecton of n-devices d: None

a:

b:

c:

d:

a:

b: NMOS in parallel and PMOS in series c: Both NMOS and PMOkar1.jpgrallel d: Both NMOS and PMOS in parallel

a: B b: A c: A+B d: AB

a: AB b: BC c: AC d: ABC

a:

b:

c: Both a & b d: None

a:

b:

c: none of the above d: Both a & b

Schematic Design Of Transistor Level NAND & NOR Gate