Schematic Design Of Transistor Level NAND & NOR Gate

  1. Draw truth table for NAND and NOR gate.
  2. Write the combinations of input for which NAND and NOR gate behaves exactly the same.
  3. How can a NAND gate can be cinverted to behave as an inverter?
  4. What are the driving volage range for n-switch and p-switch respectively?
  5. What is the advantage of making Karnaugh Map of any combinational logic?