Schematic Design Of D-Latch and D-Flip Flop
1. What frequency clock source will produce clock waveforms having a period equal to 5 us (5 microseconds)?
2. On what parameters do the output of D flip flop depend?
3. The timing diagram corresponds to: 
4. The timing diagram corresponds to 
5. Which statement is false about D latch
6. Which latch has the property of either retaining or toggling the previous value
7. Which statement below is the apt definition of flip flop
8. The above figure is the gate level implementation of:
9. What kind of flip flop is generally preffered for constructing counters?
10. What is meant by the problem of metastability in flip flop