Virtual Labs

a: 1 b: 2 c: 3 d: 4

a: AND gate b: NOT gate c: NOR gate d: NAND gate

a:

b: <

> c:

d:

a: Any difference in inputs gurantees a high output b: Any difference in inputs gurantees a low output c: A high input gives a high output d: A low input gives a high output

a:

b:

c:

d:

a:

b:

c:

d: None of these

a: V_dd/2 < V_in ≤ V_dd-V_tp b: V_in = V_dd/2 c: 0 ≤ V_in ≤ V_tn d: V_in ≥ V_dd-V_tp

a: Linear & unsaturated b: Cut-off & linear c: Linear & saturated d: Saturated & linear

a: Maximum of rise time and fall time b: Product of rise time and fall time c: Average of rise time and fall time d: Addition of rise time and fall time

a: 0 b: 1 c: 0.5 d: ∞

Schematic Design Of Transistor Level Inverter