Virtual Labs

a: Time to correctly access the input b: Time to correctly access the output c: Average rise time and fall time d: Time taken for the output to come after the input has been captured

3. The optimum size of each inverter is ________ of its neighbours

a: Geometric mean b: Arithmetic mean c: Geometric or arithmetic mean d: None of the above

4. What does Cg1 corresponds to in the following formula?

a: Input gate capacitance of the last inverter driving capacitative load b: Sum of input capacitances of all the inverter in series c: Input gate capacitance of first inverter in series d: None of the above

5. If the gate size is increased by n then what will be the effect on its resistance?

a: Increases by n b: Decreases by n c: Decreases by n2 d: Remains constant

6. If the gate size is increased by n then what will be the effect on its capacitance?

a: Increases by n2 b: Increases by n c: Decreases by n d: Remains constant

7. Choose the correct statement from the following.

a: All the inveters in series are kept to be of same size for minimum delay b: The inverter size does not matter as long as the inverter driving the load has very big size c: The inverter size does not matter as long as the inverter driving the load has very small size d: The size of the inverter driving the load is maximum of all and is some multiple of size of the previous inverters

8. For minimm delay, what is the no of inverters in the chain connected in series?

a: 4 b: 5 c: 6 d: Need to calculate according to the situation given, it is not fixed.

9. Let a be the stage ratio of an inverter chain. What is its optimum value to drive a load capacitor with minimum delay?

a: 4 b: 1/e c: 2 d: e

10. In the above question, if parasitic capacitances are taken into consideration then what is the optimum value of a?

a: 4 b: e c: 1/e d: 2

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