Computer Science & Engineering VLSI Lab Experiments

Schematic Design Of Transistor Level NAND & NOR Gate

DEFINITION OF NAND GATE

NAND gate has 1 output and 2 or more input
The output of the NAND gate is low only when all the inputs are high else it is low.
A NAND gate could be veiwed as an AND gate with inverter at the output

SCHEMATIC OF NAND GATE



Input A Input B Output
0 0 1
0 1 1
1 0 1
1 1 0

DEFINITION OF NOR GATE

NOR gate has 1 output and 2 or more input
The output of NOR gate is high only when all the inputs are low else it is high
A NOR gate could be viewed as an OR gate with inverter at the output


SCHEMATIC OF NOR GATE



Input A Input B Output
0 0 1
0 1 0
1 0 0
1 1 0