# Very Large Scale Integration Lab

• Schematic Design Of Transistor Level Inverter

In this experiment we will learn the basic design of an inverter. Inverter is the most basic component which we can make out using one NMOS and one PMOS transistor. Here you will learn about the basics how inverter works internally, how the transistor are placed inside inverter and how we get the inverted output corresponding to the inputs we provide. We will learn the layout designing and effects of capacitance and effects of width and length of transistor on the output of an inverter
• Schematic Design Of Transistor Level NAND & NOR Gate

In this experiment, we will learn about the series and parallel combination of n-switches and p-switches. Then we will proceed to the transistor level designing of NAND and NOR gate using NMOS and PMOS and also layout designing of the same.
• Schematic Design Of Transistor Level XOR & XNOR Gate

In this experiment, we will first learn how to deduce parallel and series combination of n and p-switches given a combinational logic and hence design them, specifically XOR and XNOR.
• Schematic Design Of Pass Transistor Logic & Multiplexer

Transmission gates are used in digital circuits to pass or block particular signal from the components. In transmission gates, NMOS and PMOS are parallel connected to each other. Schematic representation of transmission gate and its circuit symbol are shown below.
• Delay Estimation In Chain Of Inverters

The method of logical effort is one of the methods used to estimate delay in a CMOS circuit. The model describes delay caused by the capacitive load that the logic gate drives and by the topology of the logic gate. As the gate increases delay also increases, but delay depends on the logic function of the gate also.
• Schematic Design Of D-Latch and D-Flip Flop

Latch is an electronic device that can be used to store one bit of information. The D latch is used to capture, or latch the logic level which is present on the Data line when the clock input is high. If the data on the D line changes state while the clock pulse is high, then the output, Q, follows the input, D. When the CLK input falls to logic 0, the last state of the D input is trapped and held in the latch.
• Spice Code Platform